I read many years ago that The Art Of Electronics by Horowitz and Hill was essentially written for post graduate engineers to bridge the gap between practical application and theory of electronic principles. They did produce a separate volume with answers to questions which may be available on 'tinternet. Slightly off topic... Recently when raw graduates were interviewed for a hardware design position, I was shocked at the lack of practical ability demonstrated by degree students when asked to complete a simple test sheet. First question was a very simple five resistor network requiring nothing more than an understanding of Kirchoff or superposition theory. Only one out of twenty applicants managed to partially complete the question. HNC/HND students fared much better. Back on topic.
Dr Wobble wrote:I have a problem with the OP 807 stage loading down the LTP. The LTP has 40v RMS on each anode but is about 1v @ g1 on the 807's. I'm thinking of putting a AC coupled cathode follower in-between to stop this.
If the bias on each 807 is -30V you can not apply more than 2 x 30V Peak or 60V peak to peak and stay within class A operation. Now, if correct, 40V RMS is roughly 110V peak to peak and is way too high for class A. With a signal this large either the grids are being driven negative into cut off, but not above 0V (AB1) or additionally the grid become positive and start drawing grid current (AB2). This might account for signal degradation.
An 807 can handle these modes of operation, but the driver has to have a low output impedance for AB2 and STC data states an 807 requires a total grid circuit impedance of less than 500 ohms. Grid G1 becomes an anode when driven positive and current flows hence the need for a low impedance driver. Traditionally transformer coupling provides the correct drive impedance for this operation. Normally unless the design is operating in AB2 you do not need cathode follower drivers. What is the design criteria for your output stage and chosen class of operation? It is essential to set grid bias and drive voltage for any given mode as per valve manufacturers data.
What test frequency is being used, guess its 1kHz? With a grid leak resistor of 100k it is usual to expect a coupling capacitor value of between 0.22uF and 0.47uF. However this would not account for 40V RMS at the anode being reduced to 1V, something else is going on here. In class A operation the output valves should offer very low loading for the driver output signals. Are the 807 valves OK and reasonably matched or just simply being seriously over-driven?
One way to reduce the coupling capacitor count is to remove 6SN7 stage completely and DC couple the LTP input to the EF37A anode. You will have to adjust DC conditions for both stages but effectively only one capacitor to consider in feedback loop phase margin calculations.